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semiconductor group 55 01.95 ? 262 144 words by 4-bit organization ? fast access and cycle time 50 ns access time 95 ns cycle time (-50 version) 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) ? fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) ? low power dissipation max. 495 mw active (-50 version) max. 440 mw active (-60 version) max. 385 mw active (-70 version) max. 5.5 mw standby max. 1.1 mw standby for l-version ordering information type ordering code package description hyb 514256b-50 q67100-q1044 p-dip-20-2 dram (access time 50ns) hyb 514256b-60 q67100-q530 p-dip-20-2 dram (access time 60 ns) hyb 514256b-70 q67100-q433 p-dip-20-2 dram (access time 70 ns) hyb 514256bj-50 q67100-q1054 p-soj-26/20-1 dram (access time 50 ns) hyb 514256bj-60 q67100-q536 p-soj-26/20-1 dram (access time 60 ns) hyb 514256bj-70 q67100-q537 p-soj-26/20-1 dram (access time 70 ns) hyb 514256bl-50 on request p-dip-20-2 dram (access time 50 ns) hyb 514256bl-60 q67100-q542 p-dip-20-2 dram (access time 60 ns) hyb 514256bl-70 q67100-q543 p-dip-20-2 dram (access time 70 ns) hyb 514256bjl-50 on request p-soj-26/20-1 dram (access time 50 ns) hyb 514256bjl-60 q67100-q608 p-soj-26/20-1 dram (access time 60 ns) hyb 514256bjl-70 Q67100-Q607 p-soj-26/20-1 dram (access time 70 ns) 256 k 4-bit dynamic ram low power 256 k 4-bit dynamic ram advanced information ? single + 5 v ( 10 %) supply with a built-in v bb generator ? output unlatched at cycle end allows two- dimensional chip selection ? read-modify-write, cas-before- ras refresh, ras-only refresh, hidden-refresh and fast page mode capability ? all inputs, outputs and clocks ttl-compatible ? 512 refresh cycles/8 ms 512 refresh cycles/64 ms for l-version only ? plastic packages: p-dip-20-2, p-soj-26/20-1 hyb 514256b/bj-50/-60/-70 hyb 514256bl/bjl-50/-60/-70
semiconductor group 56 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram the hyb 514256b/bj/bl/bjl is the new generation dynamic ram organized as 262 144 words by 4-bit. the hyb 514256b/bj/bl/bjl utilizes cmos silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. multiplexed address inputs permit the hyb 514256b/bj/bl/bjl to be packaged in a standard plastic p-dip-20-2,or plastic p-soj-26/20-1. this package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. system oriented features include single + 5 v ( 10 %) power supply, direct interfacing with high-performance logic device families such as schottky ttl. these hyb 514256bl/bjl are specially selected for battery backup applications. pin definitions and functions pin no. function a0-a8 address inputs ras row address strobe oe output enable i/o1-i/o4 data input/output cas column address strobe we read/write input v cc power supply (+ 5 v) v ss ground (0 v) n.c. no connection
semiconductor group 57 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram pin configuration (top view) p-soj-26/20-1 p-dip-20-2
semiconductor group 58 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram block diagram
semiconductor group 59 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram absolute maximum ratings operating temperature range .........................................................................................0 to + 70 ? c storage temperature range......................................................................................C 55 to + 150 ?c soldering temperature .......................................................................................................... ..260 ?c soldering time ................................................................................................................. ............10 s input/output voltage ........................................................................................................ C 1 to + 7 v power supply voltage...................................................................................................... C 1 t o + 7 v power dissipation.............................................................................................................. ....... 0.6 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics t a = 0 to 70 ?c; v ss = 0 v; v cc = 5 v 10 % parameter symbol limit values unit test condition min. max. input high voltage v ih 2.4 6.5 v 1) input low voltage v il C 1.0 0.8 v 1) output high voltage ( i out = C 5 ma) v oh 2.4 C v 1) output low voltage ( i out = 4.2 ma) v ol C 0.4 v 1) input leakage current, any input (0 v v in 6.5 v, all other pins = 0 v) i i(l) C 10 10 m a 1) output leakage current (do is disabled, 0 v v out v cc ) i o(l) C 10 10 m a 1) average v cc supply current: -50 version -60 version -70 version ( ras, cas, address cycling: t rc = t rc min.) i cc1 C C C 90 80 70 ma ma ma 2) 3) 2) 3) 2) 3) standby v cc supply current ( ras = cas = v ih ) i cc2 C2maC average v cc supply current, ras only mode: -50 version -60 version -70 version ( ras cycling: cas = v ih : t rc = t rc min.) i cc3 C C C 90 80 70 ma ma ma 2) 2) 2)
semiconductor group 60 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram average v cc supply current, fast page mode: -60 version -70 version -50 version ( ras = v il , cas, address cycling: t pc = t pc min.) i cc4 C C C 70 60 50 ma ma ma 2) 3 2) 3) 2) 3) standby v cc supply current l-version ( ras = cas = v cc C 0.2 v) i cc5 C C 1 200 ma m a 1) 1) average v cc supply current, cas-before-ras refresh mode: -50 version -60 version -70 version ( ras, cas cycling: t rc = t rc min.) i cc6 C C C 90 80 70 ma ma ma 2) 2) 2) for l-version only: battery backup current: average power supply current, battery backup mode: ( cas = cas before ras cycling or 0.2 v, oe = v cc C 0.2 v we = v cc C 0.2 v or 0.2 v, a0 to a8 = v cc C 0.2 v or 0.2 v, i/o1 to i/o4 = v cc C 0.2 v or 0.2 v or open, t rc = 125 m s, t ras = t ras min. ~ 1 m s) i cc7 C 300 m a 2) dc characteristics (contd) t a = 0 to 70 ?c; v ss = 0 v; v cc = 5 v 10 % parameter symbol limit values unit test condition min. max.
semiconductor group 61 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram ac characteristics 4) 13) t a = 0 to 70 ?c; v cc = 5 v 10 %; t t = 5 ns parameter symbol limit values unit -50 -60 -70 min. max. min. max. min. max. random read or write cycle time t rc 95 C 110 C 130 C ns read-modify-write cycle time t rwc 140 C 160 C 185 C ns fast page mode cycle time t pc 35 C 40 C 45 C ns fast page mode read-modify- write cycle time t prwc 80 C 90 C 100 C ns access time from ras 6) 11) t rac C50 C60 C70 ns access time from cas 6) 11) t cac C15 C15 C20 ns access time from column address 6) 12) t aa C25 C30 C35 ns access time from cas precharge 6) 12) t cpa C30 C35 C40 ns cas to output in low-z 4) t clz 0C 0C 0C ns output buffer turn-off delay 7) t off 015 020 020 ns transition time (rise and fall) 5) t t 350 350 350 ns ras precharge time t rp 35 C 40 C 50 C ns ras pulse width t ras 50 10.000 60 10.000 70 10.000 ns ras pulse width (fast page mode) t rasp 50 100.000 60 100.000 70 100.000 ns ras hold time t rsh 15 C 15 C 20 C ns cas hold time t csh 50 C 60 C 70 C ns cas pulse width t cas 15 10.000 15 10.000 20 10.000 ns ras hold time from cas precharge (fast page mode) t rhcp 30 C 35 C 45 C ns cas precharge to we delay time (fpm rmw) t cpwd 55 C 60 C 65 C ns ras to cas delay time 11) t rcd 20 35 20 45 20 50 ras to column address delay time 12) t rad 15 25 15 30 15 35 ns cas to ras precharge time t crp 5C 5C 5C ns cas precharge time t cp 10 C 10 C 10 C ns
semiconductor group 62 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram row address setup time t asr 0C 0C 0C ns row address hold time t rah 10 C 10 C 10 C ns column address setup time t asc 0C 0C 0C ns column address hold time t cah 10 C 15 C 15 C ns column address to ras lead time t ral 25 C 30 C 35 C ns read command setup time t rcs 0C 0C 0C ns read command hold time 8) t rch 0C 0C 0C ns read command hold time referenced to ras 8) t rrh 0C 0C 0C ns write command hold time t wch 10 C 10 C 15 C ns write command pulse width t wp 10 C 10 C 15 C ns write command to ras lead time t rwl 15 C 15 C 20 C ns write command to cas lead time t cwl 15 C 15 C 20 C ns data setup time 9) t ds 0C 0C 0C ns data hold time 9) t dh 10 C 15 C 15 C ns refresh period t ref C8 C8 C8 ms refresh period l-version t ref C64 C64 CC ms write command setup time 10) t wcs 0C 0C 0C ns cas to we delay time 10) t cwd 40 C 45 C 50 C ns ras to we delay time 10) t rwd 75 C 90 C 100 C ns column address to we delay time 10) t awd 50 C 60 C 65 C ns cas setup time ( cas-before- ras cycle) t csr 5C 5C 5C ns cas hold time ( cas-before- ras cycle) t chr 10 C 15 C 15 C ns ras to cas precharge time t rpc 0C 0C 0C ns ac characteristics (contd) 4) 13) t a = 0 to 70 ?c; v cc = 5 v 10 %; t t = 5 ns parameter symbol limit values unit -50 -60 -70 min. max. min. max. min. max.
semiconductor group 63 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram cas precharge time ( cas- before- ras counter test cycle) t cpt 25 C 30 C 40 C ns oe access time t oea C15 C15 C20 ns ras hold time referenced to oe t roh 10 C 10 C 10 C ns output buffer turn-off delay time from oe t oez 015 020 020 ns data to cas low delay 14) t dzc 0C 0C 0C ns cas high to data delay 15) t dzo 0C 0C 0C oe high to data delay 15) t cdd 15 C 20 C 20 C ns oe to data delay 15) t odd 15 C 20 C 20 C ns capacitance t a = 0 to 70 ?c; v cc = 5 v 10 %; f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a8) c i1 C5pf input capacitance ( ras, cas, we, oe) c i2 C7pf output capacitance (i/o1 ... i/o4) c 5o C7pf ac characteristics (contd) 4) 13) t a = 0 to 70 ?c; v cc = 5 v 10 %; t t = 5 ns parameter symbol limit values unit -50 -60 -70 min. max. min. max. min. max.
semiconductor group 64 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram notes : 1) all voltages are referenced to v ss . 2) i cc1 , i cc3 , i cc4 , i cc6 and i cc7 depend on cycle rate. 3) i cc1 and i cc4 depend on output loading. specified values are measured with the output open. 4) an initial pause of 200 m s is required after power-up followed by 8 ras cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas-before- ras initialization cycles instead of 8 ras cycles are required. 5) v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are also measured between v ih and v il . 6) measured with a load equivalent to 2 ttl loads and 100 pf. 7) t off (max.) and t oez (max.) define the time at which the output achieves the open-circuit conditions and is not referenced to output voltage levels. 8) either t rch or t rrh must be satisfied for a read cycle. 9) these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-modify-write cycles. 10) t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read-modify-write cycle and i/o will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of i/o (at access time) is indeterminate. 11) operation within the t rcd (max.) limit insures that t rac (max.) can be met, t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 12) operation within the t rad (max.) limit insures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 13) ac measurements assume t t = 5ns. 14) either t dzc or t dzo must be satisfied. 15) either t cdd or t odd must be satisfied.
semiconductor group 65 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram waveforms read cycle row address column address row address valid data out ras cas a0 - a8 we oe i/o1-i/o4 (inputs) i/o1-i/o4 (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z h or l
semiconductor group 66 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram write cycle (early write) t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column address address row row address t rah t wcs h or l ras cas a0 - a8 we oe i/o1-i/o4 (inputs) i/o1-i/o4 (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr
semiconductor group 67 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram write cycle ( oe controlled write) valid data t rwl t wp t oeh t odd t cwl t dzo t oea t clz t ds t oez t dh t rc v ih v il row address t dzc h or l hi-z hi-z column address address row t asc t rad t ral t cah t rah ras cas a0 - a8 we oe i/o1-i/o4 (inputs) i/o1-i/o4 (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr
semiconductor group 68 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram read-write (read-modify-write) cycle row address row address t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o1-i/o4 (outputs) v oh v ol v ih v il v ih v il i/o1-i/o4 (inputs) oe we v ih v il t asr column address t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac h or l t asc v ih v il v ih v il ras cas a0 - a8 v ih v il
semiconductor group 69 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram fast page mode read-modify-write cycle t cah t cp t dzc t dzo t rac t cac t clz t rcs t aa t oea t rcd t rad t rah t asr t asc t cas t cas t prwc t cwd t cah t asc t cas t rsh t rp t crp t asr t cah t asc t ral t cwd t rwd t cwl t cwl t cwd t awd t awd t wp t wp t cwl t rwl t awd t wp t odd t oeh t dh t ds t cpa t oez t clz t dzc t aa t cac t oea t ds t oez t dh t oeh t aa t odd t dzc t cpa t oea t clz t ds t dh t oeh t odd ras v ih v il cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol we oe i/o1-i/o4 (inputs) i/o1-i/o4 (outputs) data in data in data in data out out data data out address row column address address column address row address t rasp t csh column t cpwd t cpwd h or l a0-a8 t oez
semiconductor group 70 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram fast page mode read cycle t rasp t cas t cas t pc t cp t rcd t csh t cah t cah t asc t asc t asr t rah t rad t rcs t rcs t rcs t asc t cah t cas t rsh t crp t rp t asr t rch t cpa t oea t oea t aa t aa t dzc t dzc t cdd t rrh t cpa t oea t aa t dzc t dzo t odd t odd t dzo t odd t dzo t off t oez t oez t off t oez t cac t cac t clz t clz t clz t off t rac t cac valid data out data out data out valid valid column address address addr address column row row ras i/o1-i/o4 (outputs) i/o1-i/o4 (inputs) oe we a0-a8 cas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il h or l t rhcp t rch v oh v ol column address
semiconductor group 71 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram fast page mode early write cycle t rasp t rp t rsh t cas t cas t cp t crp t ral t cah t asr t cwl t rwl t cah t asc t asc t cwl t cwl t wcs t wcs t wcs t wch t wp t wp t wch t wp t wch t rad t cas t rcd t pc t cah t rah t asr t asc t dh t ds t ds t dh t dh t ds column address address address column row row addr valid data in valid valid data in data in column address hi-z ras i/o1-i/o4 (outputs) i/o1-i/o4 (inputs) oe we a0-a8 cas v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il h or l v oh v ol
semiconductor group 72 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram ras-only refresh cycle t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row address row address hi-z a0-a8 ras cas i/o1-i/o4 (outputs) h or l
semiconductor group 73 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram cas-before- ras refresh cycle t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h or l ras i/o1-i/o4 (outputs) i/o1-i/o4 (inputs) oe we cas v oh v ol
semiconductor group 74 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram hidden refresh cycle (read) ras i/o1-i/o4 (outputs) i/o1-i/o4 (inputs) oe we a0-a8 cas t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh h or l valid data out row address column address row addr hi-z v oh v ol
semiconductor group 75 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram hidden refresh cycle (early write) ras i/o1-i/o4 (outputs) i/o1-i/o4 (inputs) oe we v ih v il a0-a8 v ih v il v ih v il v ih v il cas v ih v il v ih v il h or l t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc address row addr row address valid data hi-z column v oh v ol
semiconductor group 76 hyb 514256b/bl/bj/bjl-50/-60/-70 256 k 4-dram h or l t csr t asr t asc t chr t cpt t wrp t ral t cah t rsh t rp t ras t cas t rcs t cdd t cac t aa t wrh t oea t odd t clz t dzc t dzo t oez t off t rwl t cwl t wch t wcs t wrh t wrp t ds t odd t dh t wrh t wrp t oez t rwl t cwl t awd t cwd t wp t rcs t cac t oea t oeh t aa t clz t dh t dzo t ds t dzc t cac v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il i/o1-i/o4 (inputs) ras i/o1-i/o4 (inputs) oe we a0-a8 cas i/o1-i/o4 (outputs) i/o1-i/o4 (outputs) i/o1-i/o4 (inputs) we oe we oe i/o1-i/o4 (outputs) column address row address data in valid data out valid data in hi-z hi-z hi-z read cycle read-modify-write cycle write cycle t rrh t rch d.out

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